1. Technical Field
The present invention relates to a test apparatus, a test method, a calculating apparatus and a computer-readable medium. More particularly, the present invention relates to a test apparatus, a test method, a calculating apparatus and a computer-readable medium which calculate a remedy solution for a defective storage cell in a memory under test.
2. Related Art
FIG. 5 illustrates the configuration of a conventional test apparatus 100 which calculates a remedy solution for replacing a defective storage cell in a semiconductor memory with a backup cell (for example, see Non-patent Document 1).
The test apparatus 100 includes therein a plurality of test signal feeding sections 120, a plurality of defect detecting sections 130, a plurality of fail memories 140, and a plurality of calculating sections 150. Each of the test signal feeding sections 120 feeds a test signal to a corresponding one of a plurality of memories under tests 110. Each of the defect detecting sections 130 detects information identifying a defective storage cell in a corresponding one of the memories under test 110 (fail information) with reference to the data read from the corresponding memory under test 110 in response to the test signal, and writes the detected fail information into a corresponding one of the fail memories 140. The fail information written on each of the fail memories 140 is transferred to a corresponding one of the calculating sections 150 on completion of the test on a corresponding one of the memories under test 110. Each of the calculating sections 150 obtains a remedy solution for a corresponding one of the memories under test 110 with reference to the fail information transferred thereto. Here, the calculating sections 150 perform the processing to obtain the remedy solutions while the test signal feeding sections 120 and the defect detecting sections 130 perform tests.
Non-patent Document 1: Jin-Fu Li and 6 other members, “A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy”, INTERNATIONAL TEST CONFERENCE, INTERNATIONAL TEST CONFERENCE 2003 PROCEEDINGS, Sep. 30, 2003, p. 393-402
FIG. 6 is a timing chart illustrating the processing timings seen when the conventional test apparatus 100 tests a group of memories under test 110 during one test session.
The test apparatus 100 requires a different duration to calculate a remedy solution for each of the memories under test 110. Therefore, even if each calculating section 150 concurrently starts the calculation for a corresponding one of the memories under test 110, each calculating section 150 finishes the calculation at a different timing. Furthermore, since the remedy solution calculations are NP-complete, it is not known in advance how long the test apparatus 100 will require in order to complete the calculations. For these reasons, one or more of the calculating sections 150 may not complete the calculations by the time the test signal feeding sections 120 and the defect detecting sections 130 finish the tests which are performed in parallel.
Here, until the calculating sections 150 complete the current calculations, the pieces of fail information written in the fail memories 140 are not transferred to the calculating sections 150. Therefore, the defect detecting sections 130 can not start the tests on the next group of memories under test 110 until the calculating sections 150 finish the current calculations. Here, consider a case where the test apparatus 100 tests a group of memories under test 110 during each test session. In this case, if the test apparatus 100 takes a relatively long time to calculate a remedy solution for any one of the memories under test 110 in the tested group, the test apparatus 100 can start testing none of the memories under test 110 included in the next group until completing the relatively lengthy calculation. This means a longer waiting time X from the end of the current tests to the start of the next tests. As a result, the test apparatus 100 suffers from a lowered throughput.